iverilog 10.3 FPGA Verilog simulation and synthesis tool
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by vvp
. For synthesis, the compiler generates netlists in the desired format.
- Website: http://iverilog.icarus.com/
- License: GPL 2, LGPL 2.1+
- Package source: fpga.scm
- Patches: None
- Builds: x86_64-linux, i686-linux